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ISL5416
Tables of Channel Indirect Write Address Registers
The response of the channels to the SYNCIn1 and SYNCIn2
inputs is controlled by IWA *000h. Bits 31:16 control the
response to SYNCIn2 and bits 15:0 control the response to
SYNCIn1. Most processing blocks can be individually reset
by a SYNC. Some control registers are double buffered with
the uP loading a master register and the data transfer to a
slave/active register occurring on either a write to a strobe
IWA location or on a SYNCInX signal. Updating with a
SYNCInX signal allows the functions in more than one
ISL5416 to be updated simultaneously.
SET BITS TO 1 TO ENABLE.
.
TABLE 51. CHANNEL RESET/SYNCIn1, SYNCIn2 CONTROL (IWA = *000h) RESET STATE = 0x00000000h
P(31:0)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
FUNCTION
CHANNEL SYNCIn2 ENABLE. Enables channel overall response to SYNCIn2.
RESERVED. Set to 0.
SERIAL OUTPUT. Reset the serial output section on SYNCIn2. This will reset the serial clock divider if GWA = 0000h, bit 29 is set.
FIFO. Reset the FIFO at the IHBF/Resampler input on SYNCIn2.
LEAP COUNTER. Reset the IHBF/Resampler leap counter on SYNCIn2.
RESAMPLER NCOs. Reset back end - resampler NCOs on SYNCIn2.
FIFO/INTERPOLATION HALF BAND FILTER/RESAMPLER. Reset back end (Interpolation Half Band Filter, Resampler, Decimation
Counter, and FIFO) on SYNCIn2.
AGC RESET. Resets AGC processing on SYNCIn2 and sets the AGC gain to 0 dB (or to the lower limit if greater than 0 dB).
AGC TIMING. Resets AGC timing on SYNCIn2.
FIR2 RESET. Resets FIR2 on SYNCIn2. Resets the datapath registers and decimation counter.
FIR1 RESET. Resets FIR1 on SYNCIn2. Resets the datapath registers and decimation counter.
CIC RESET. Resets the CIC on SYNCIn2.
RESAMPLER UPDATE. Update (start) the resampler NCOs frequency from the master/holding register to the slave/active register
on SYNCIn2.
AGC GAIN LOAD. Update/load AGC gain from the master/holding register to the slave/active register on SYNCIn2.
CARRIER CENTER FREQUENCY UPDATE. Updates Carrier Center Frequency from the master/holding register to the slave/active
register on SYNCIn2.
DATA PATH UPDATE. Update channel processing control register (*001) from the master/holding register to the slave/active
register on SYNCIn2.
CHANNEL SYNCIn1 ENABLE. Enables channel overall response to SYNCIn1.
RESERVED. Set to 0.
SERIAL OUTPUT. Reset the serial output section on SYNCIn1. This will reset the serial clock divider if GWA = 0000h, bit 29 is set.
FIFO. Reset the FIFO at the IHBF/Resampler input on SYNCIn1.
LEAP COUNTER. Reset the IHBF/Resampler leap counter on SYNCIn1.
RESAMPLER NCOs. Reset back end - resampler NCOs on SYNCIn1.
FIFO/INTERPOLATION HALF BAND FILTER/RESAMPLER. Reset back end (Interpolation Half Band Filter, Resampler, Decimation
Counter, and FIFO) on SYNCIn1.
AGC RESET. Resets AGC processing on SYNCIn1 and sets the AGC gain to 0 dB (or to the lower limit if greater team 0 dB).
AGC TIMING. Resets AGC timing on SYNCIn1.
FIR2 RESET. Resets FIR2 on SYNCIn1. Resets the datapath registers and decimation counter.
FIR1 RESET. Resets FIR1 on SYNCIn1. Resets the datapath registers and decimation counter.
CIC RESET. Resets the CIC on SYNCInq1.
RESAMPLER UPDATE. Update (start) resampler NCOs frequency from the master/holding register to the slave/active register on
SYNCIn1.
47
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